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nonvolatile memory, quad 64-position digital potentiometer ad5233 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2008 analog devices, inc. all rights reserved. features nonvolatile memory stores wiper setting 4-channel independent programmable 64-position resolution power-on refreshed with eemem settings eemem restore time: 140 s typical full monotonic operation 10 k, 50 k, and 100 k terminal resistance permanent memory write protection wiper setting readback predefined linear increment/decrement instructions predefined 6 db/step log taper increment/decrement instructions spi-compatible serial interface with readback function 2.7 v to 5.5 v single supply or 2.5 v dual supply 11 bytes extra nonvolatile memory for user-defined data 100-year typical data retention, t a = 55c applications mechanical potentiometer replacement instrumentation: gain, offset adjustment programmable voltage-to-current conversion programmable filters, delays, time constants programmable power supply sensor calibration functional block diagram o1 addr decode ad5233 sdi serial interface cs clk sdi sdo sdo pr wp rdy eemem control rdac1 register v dd 11 bytes user eemem digital 5 register digital output buffer o2 eemem5 rdac1 w1 b1 a1 v ss rdac2 register eemem2 eemem1 rdac3 register eemem3 rdac4 register eemem4 rdac2 w2 b2 a2 rdac3 w3 b3 a3 rdac4 w4 b4 a4 2 gnd 02794-001 figure 1. general description the ad5233 is a quad-channel nonvolatile memory, 1 digitally controlled potentiometer 2 with a 64-step resolution. the device performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid-state reliability, and remote controllability. the ad5233 has versatile program- ming using a serial peripheral interface (spi) for 16 modes of operation and adjustment, including scratchpad programming, memory storing and restoring, increment/decrement, 6 db/step log taper adjustment, wiper setting readback, and extra eemem for user-defined information such as memory data for other components, look-up tables, or system identification information. 1 the terms nonvolatile memory an d eemem are used interchangeably. 2 the terms digital potentiometer and rdac are used interchangeably. in the scratchpad programming mode, a specific setting can be programmed directly to the rdac register, which sets the resistance between terminal w to terminal a and terminal w to terminal b. this setting can be stored into the eemem and is transferred automatically to the rdac register during system power-on. the eemem content can be restored dynamically or through external pr strobing. a wp function protects eemem contents. to simplify the programming, independent or simultaneous increment or decrement commands can be used to move the rdac wiper up or down, one step at a time. for logarithmic 6 db step changes in wiper settings, the left or right bit shift command can be used to double or halve the rdac wiper setting. the ad5233 is available in a thin 24-lead tssop package. the part is guaranteed to operate over the extended industrial temperature range of ?40c to +85c.
ad5233 rev. b | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics10 k, 50 k, and 100 k versions .......................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 test circuits ..................................................................................... 13 theory of operation ...................................................................... 15 scratchpad and eemem programming .................................. 15 basic operation .......................................................................... 15 eemem protection .................................................................... 16 digital input/output configuration ........................................ 16 serial data interface ................................................................... 16 daisy-chain operation ............................................................. 17 terminal voltage operation range ......................................... 17 power-up sequence ................................................................... 17 latched digital outputs ............................................................ 17 advanced control modes ......................................................... 19 rdac structure.......................................................................... 20 programming the variable resistor ......................................... 20 programming the potentiometer divider ............................... 21 programming examples ............................................................ 21 flash/eemem reliability .......................................................... 22 applications information .............................................................. 23 bipolar operation from dual supplies.................................... 23 gain control compensation .................................................... 23 high voltage operation ............................................................ 23 dac .............................................................................................. 23 bipolar programmable gain amplifier ................................... 24 programmable low-pass filter ................................................ 24 programmable state-variable filter ......................................... 25 programmable oscillator .......................................................... 26 programmable voltage source with boosted output ........... 26 programmable current source ................................................ 27 programmable bidirectional current source ......................... 27 resistance scaling ...................................................................... 27 doubling the resolution ........................................................... 28 r e s i st a nc e to l e r anc e, d r i f t , a n d te mp e r atu re mi s m atch considerations ............................................................................ 28 rdac circuit simulation model ............................................. 28 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 29 revision history 5/08rev. a to rev. b changes to features ........................................................................... 1 changes to table 1 ............................................................................. 3 changes figure 3 ............................................................................... 6 changes to absolute maximum ratings section .......................... 7 changes to figure 17 and figure 18 .............................................. 11 changes to programmable oscillator section ............................. 26 changes to ordering guide ........................................................... 29 7/04rev. 0 to rev. a format updated .................................................................. universal changes to features, general description, and block diagram .............................................................................................. 1 changes to specifications ................................................................. 3 replaced timing diagrams .............................................................. 6 changes to absolute maximum ratings ........................................ 7 changes to pin function descriptions ........................................... 8 replaced figure 11 ............................................................................ 9 added test circuit (figure 36) ...................................................... 13 changes to theory of operation ................................................... 14 changes to applications ................................................................. 22 updated outline dimensions ........................................................ 28 changes to ordering guide ........................................................... 28 3/02revision 0: initial version
ad5233 rev. b | page 3 of 32 specifications electrical characteristics10 k, 50 k, and 100 k versions v dd = 3 v 10% or 5 v 10%, v ss = 0 v, v a = v dd , v b = 0 v, ?40c < t a < +85c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristics, rheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = nc, monotonic ?0.5 0.1 +0.5 lsb resistor integral nonlinearity 2 r-inl r wb , v a = nc ?0.5 0.1 +0.5 lsb nominal resistor tolerance ?r ab /r ab d = 0x3f ?40 +20 % resistance temperature coefficient (?r wb /r wb )/?t 10 6 600 ppm/c wiper resistance r w i w = 100 a, code = half scale 15 100 dc characteristics, potentiometer divider mode resolution n 6 bits differential nonlinearity 3 dnl monotonic ?0.5 +0.1 +0.5 lsb integral nonlinearity 3 inl ?0.5 +0.1 +0.5 lsb voltage divider temperature coefficient (?v w /v w )/?t 10 6 code = half scale 15 ppm/c full-scale error v wfse code = full scale ?1.5 0 % fs zero-scale error v wzse code = zero scale 0 1.5 % fs resistor terminals terminal voltage range 4 v a , v b , v w v ss v dd v capacitance a, capacitance b 5 c a , c b f = 1 mhz, measured to gnd, code = half scale 35 pf capacitance w 5 c w f = 1 mhz, measured to gnd, code = half scale 35 pf common-mode leakage current 5 , 6 i cm v w = v dd /2 0.015 1 a digital inputs and outputs input logic high v ih with respect to gnd, v dd = 5 v 2.4 v with respect to gnd, v dd = 3 v 2.1 v with respect to gnd, v dd = 2.5 v, v ss = ?2.5 v 2.0 v input logic low v il with respect to gnd, v dd = 5 v 0.8 v with respect to gnd, v dd = 3 v 0.6 v with respect to gnd, v dd = 2.5 v, v ss = ?2.5 v 0.5 v output logic high (sdo, rdy) v oh r pull-up = 2.2 k to 5 v (see figure 35 ) 4.9 v output logic low v ol i ol = 1.6 ma, v logic = 5 v (see figure 35 ) 0.4 v input current i il v in = 0 v or v dd 2.5 a input capacitance 5 c il 4 pf output current 5 i o1 , i o2 v dd = 5 v, v ss = 0 v, t a = 25c, sourcing only 50 ma v dd = 2.5 v, v ss = 0 v, t a = 25c, sourcing only 7 ma
ad5233 rev. b | page 4 of 32 parameter symbol conditions min typ 1 max unit power supplies single-supply power range v dd v ss = 0 v 2.7 5.5 v dual-supply power range v dd /v ss 2.5 2.75 v positive supply current i dd v ih = v dd or v il = gnd 3.5 10 a negative supply current i ss v ih = v dd or v il = gnd, v dd = 2.5 v, v ss = ?2.5 v 0.55 10 a eemem store mode current i dd (store) v ih = v dd or v il = gnd, v ss = 0, i ss 0 40 ma i ss (store) v dd = 2.5 v, v ss = ?2.5 v ?40 ma eemem restore mode current 7 i dd (restore) v ih = v dd or v il = gnd, v ss = gnd, i ss 0 0.3 3 9 ma i ss (restore) v dd = 2.5 v, v ss = ?2.5 v ?0.3 ?3 ?9 ma power dissipation 8 p diss v ih = v dd or v il = gnd 0.018 0.05 mw power supply sensitivity 5 p ss ?v dd = 5 v 10% 0.002 0.01 %/% dynamic characteristics 5 , 9 bandwidth bw ?3 db, r ab = 10 k/50 k/100 k 630/135/66 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k 0.04 % v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 50 k, 100 k 0.015 % v w settling time t s v a = v dd , v b = 0 v, v w = 0.50% error band, code 0x000 to code 0x200 for r ab = 10 k/50 k/100 k 0.6/2.2/3.8 s resistor noise voltage e n_wb r wb = 5 k, f = 1 khz 9 nv/hz crosstalk (c w1 /c w2 ) c t v a = v dd , v b = 0 v, measure v w with adjacent rdac making the full-scale code change ?1 nv/sec analog crosstalk (c w1 /c w2 ) c ta v dd = v a1 = +2.5 v, v ss = v b1 = ?2.5 v, measure v w1 with v w2 = 5 v p-p @ f = 10 khz, code 1 = 0x20, code 2 = 0x3f, r ab = 10 k/ 50 k/100 k ?86/?73/?68 db 1 typicals represent averag e readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error (r-inl) is the deviatio n from an ideal value measured be tween the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. i w > 50 a @ v dd = 2.7 v for the r ab = 10 k version, i w > 50 a for the r ab = 50 k, and i w > 25 a for the r ab = 100 k version (see figure 25). 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output adc. v a = v dd and v b = v ss . dnl specification limits of ?1 lsb minimum are guaranteed monotonic op erating conditions (see figure 26). 4 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. dual-supply operation enables ground- referenced bipolar signal adjustment. 5 guaranteed by design and not subject to production test. 6 common-mode leakage current is a measure of the dc leakage from terminal b and ter minal w to a common-mode bias level of v dd /2. 7 eemem restore mode current is not continuou s. current is consumed whil e eemem locations are read an d transferred to the rdac r egister (see figure 22). to minimize power dissipation, a nop instruction should be issued immediately after instruction 1 (0x1). 8 power dissipation is calculated by p diss = (i dd v dd ) + (i ss v ss ). 9 all dynamic characteristics use v dd = 2.5 v and v ss = ?2.5 v.
ad5233 rev. b | page 5 of 32 timing characteristics v dd = 3 v to 5.5 v, v ss = 0 v, and ?40c < t a < +85c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit interface timing characteristics 2, 3 clock cycle time (t cyc ) t 1 20 ns cs setup time t 2 10 ns clk shutdown time to cs rise t 3 1 t cyc input clock pulse width t 4 , t 5 clock level high or low 10 ns data setup time t 6 from positive clk transition 5 ns data hold time t 7 from positive clk transition 5 ns cs to sdo-spi line acquire t 8 40 ns cs to sdo-spi line release t 9 50 ns clk to sdo propagation delay 4 t 10 r pull-up = 2.2 k, c l < 20 pf 50 ns clk to sdo data hold time t 11 r p = 2.2 k, c l < 20 pf 0 ns cs high pulse width 5 t 12 10 ns cs high to cs high 5 t 13 4 t cyc rdy rise to cs fall t 14 0 ns cs rise to rdy fall time t 15 0.1 0.15 ms read/store to nonvolatile eemem 6 t 16 applies to instruction 0x2, instruction 0x3, and instruction 0x9 25 ms cs rise to clock rise/fall setup t 17 10 ns preset pulse width (asynchronous) t prw not shown in timing diagram 50 ns preset response time to wiper setting t presp pr pulsed low to refresh wiper positions 70 s power-on eemem restore time t eemem1 r ab = 10 k 140 s flash/ee memory reliability endurance 7 100 kcycles data retention 8 100 years 1 typicals represent averag e readings at 25c and v dd = 5 v. 2 guaranteed by design and not subject to production test. 3 see the timing diagrams (figure 2 and figur e 3) for the location of the measured valu es. all input control voltages are specif ied with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. swit ching characteristics ar e measured using both v dd = 3 v and v dd = 5 v. 4 propagation delay depends on the value of v dd , r pull-up , and c l . 5 valid for commands that do no t activate the rdy pin. 6 the rdy pin is low only for command 2, comman d 3, command 8, command 9, command 10, and the pr hardware pulse: cmd_8 > 1 ms; cmd_9, cmd_10 > 0.12 ms; cmd_2, cmd_3 > 20 ms. device operation at t a = ?40c and v dd < 3 v extends the save time to 35 ms. 7 endurance is qualified to 100,000 cycles per jedec standard 22, me thod a117, and measured at ?40 c, +25c, and +85c; typical endurance at 25c is 700,000 cycles. 8 retention lifetime equivalent at junction temperature (t j ) = 55c per jedec standard 22, method a117. retention lifetime base d on an activation energy of 0.6 ev derates with junction temp erature, as shown in figure 45 in the flash/eemem reliability section.
ad5233 rev. b | page 6 of 32 rdy sdo cpha = 1 b15 b0 b16* *extra bit that is not defined, but normally lsb of character previously transmitted. the cpol = 1 microcontroller command aligns the incoming data to the positive edge of the clock. clk cpol = 1 t 2 t 1 t 5 t 10 t 8 t 14 t 11 t 9 t 15 t 16 t 17 t 13 t 12 t 3 t 4 b15 (msb) b0 (lsb) b15 (msb) b0 (lsb) sdi high or low high or low t 6 t 7 cs 02794-002 figure 2. cpha = 1 timing diagram clk cpol = 0 sdo b15 (msb) b0 (lsb) b15 (msb out) b0 (lsb) b15 b0 high or low high or low sdi rdy cpha = 0 * not defined, but normally msb of character previously received. the cpol = 0 microcontroller command aligns the incoming data to the positive edge of the clock. * cs t 2 t 1 t 4 t 5 t 7 t 6 t 10 t 8 t 14 t 11 t 9 t 12 t 3 t 13 t 17 t 15 t 16 02794-003 figure 3. cpha = 0 timing diagram
ad5233 rev. b | page 7 of 32 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd C0.3 v to +7 v v ss to gnd +0.3 v to ?7 v v dd to v ss 7 v v a , v b , v w to gnd v ss ? 0.3 v to v dd + 0.3 v i a , i b , i w pulsed 1 20 ma continuous 2 ma digital inputs and output voltage to gnd ?0.3 v to v dd + 0.3 v operating temperature range 2 ?40c to +85c maximum junction temperature (t j max) 150c storage temperature range ?65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec thermal resistance junction-to-ambient, ja 3 50c/w package power dissipation (t j max ? t a )/ ja stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 maximum terminal current is bounde d by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 includes programming of nonvolatile memory. 3 thermal resistance (jedec 4-layer (2s2p) board).
ad5233 rev. b | page 8 of 32 pin configuration and fu nction descriptions 1 clk sdi sdo v ss gnd a1 rdy v dd a4 w4 o1 w1 o2 b4 b1 a3 a2 w3 w2 b3 b2 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ad5233 top view (not to scale) cs pr wp 02794-005 figure 4. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 o1 nonvolatile digital output 1. address (o1) = 0x4, the data bit position is d0; defaults to logic 1 initially. 2 clk serial input register clock pin. shifts in one bit at a time on positive clock edges. 3 sdi serial data input pin. shifts in one bit at a time on positive clk edges. msb loaded first. 4 sdo serial data output pin. serves readback and daisy-chain functions. command 9 and command 10 activate the sdo output for the readback function, delayed by 16 or 17 clock pulses, depending on the clock polarity before and after the data-word (see figure 2 , figure 3 , and table 7 ). in other commands, the sdo shifts out the previously loaded sdi bit pattern, delayed by 16 or 17 clock pulses, depending on the clock polarity (see figure 2 and figure 3 ). this previously shifted-out sdi can be used for daisy- chaining multiple devices. whenever sdo is used, a pull-up resistor in the range of 1 k to 10 k is needed. 5 gnd ground pin, logic ground reference. 6 v ss negative supply. connect to 0 v for single-supply applications. if v ss is used in dual supply, it must be able to sink 40 ma for 25 ms when storing data to eemem. 7 a1 terminal a of rdac1. 8 w1 wiper terminal of rdac1, address (rdac1) = 0x0. 9 b1 terminal b of rdac1. 10 a2 terminal a of rdac2. 11 w2 wiper terminal of rdac2, address (rdac2) = 0x1. 12 b2 terminal b of rdac2. 13 b3 terminal b of rdac3. 14 w3 wiper terminal of rdac3, address (rdac3) = 0x2. 15 a3 terminal a of rdac3. 16 b4 terminal b of rdac4. 17 w4 wiper terminal of rdac4, address (rdac4) = 0x3. 18 a4 terminal a of rdac4. 19 v dd positive power supply pin. 20 wp optional write protect pin. when active low, wp prevents any changes to the present contents, except pr strobe and instruction 1 and instruction 8, and refreshes the rdac register from eemem. execute a nop instruction before returning to wp high. tie wp to v dd if not used. 21 pr optional hardware override preset pin. refreshes the sc ratchpad register with current contents of the eemem register. factory default loads midscale 0x20 until eemem is loaded with a new value by the user. pr is activated at the logic 1 transition. tie pr to v dd if not used. 22 cs serial register chip select active low. serial register operation takes place when cs returns to logic 1. 23 rdy ready. active-high open-drain output. identifies completion of software instruction 2, software instruction 3, software instruction 8, software instruction 9, software instruction 10, and hardware instruction pr . 24 o2 nonvolatile digital output 2. address (o2) = 0x4, th e data bit position is d1; defaults to logic 1 initially.
ad5233 rev. b | page 9 of 32 typical performance characteristics code (decimal) 0.20 01 63 2 0.10 ?0.10 ?0.20 48 0.15 0.05 0 ?0.05 ?0.15 6 4 r-dnl (lsb) v dd = 5v, v ss = 0v t a =+25c t a =?40c t a =+85c 0 2794-009 code (decimal) inl error (lsb) 0.20 01 63 2 0.10 0 ?0.10 ?0.20 48 0.15 0.05 ?0.05 ?0.15 6 4 t a =+25c t a =?40c t a =+85c 02794-006 figure 5. inl error vs. code, t a = ?40c, +25c, +85c overlay, r ab = 10 k figure 8. r-dnl vs. code, t a = ?40c, +25c, +85c overlay, r ab = 10 k code (decimal) dnl error (lsb) 0.20 0 16 32 64 0.10 ?0.10 ?0.20 48 0.15 0.05 0 ?0.05 ?0.15 t a =+25c t a =?40c t a =+85c 02794-007 code (decimal) 3000 0 16 32 64 2000 1000 0 48 2500 1500 500 rheostat mode tempco (ppm/c) v dd = 5v, v ss = 0v t a = ?40c to +85c 0 2794-010 figure 9. (?r wb /r wb )/?t 10 6 figure 6. dnl error vs. code, t a = ?40c, +25c, +85c overlay, r ab = 10 k code (decimal) 300 01 63 2 100 0 48 200 potentiometer mode tempco (ppm/c) v dd = 5.5v, v ss = 0v t a = ?40c to +85c v a = 2v v b = 0v 02794-011 code (decimal) r-inl (lsb) 0.20 01 63 2 0.10 ?0.10 ?0.20 48 0.15 0.05 0 ?0.05 ?0.15 6 4 v dd = 5v, v ss = 0v t a =+25c t a =?40c t a =+85c 02794-008 6 4 figure 10. (?v w /v w )/?t 10 6 vs. code, r ab = 10 k figure 7. r-inl vs. code, t a = ?40c, +25c, +85c overlay, r ab = 10 k
ad5233 rev. b | page 10 of 32 code (decimal) 80 0 16 32 64 40 0 48 60 20 r w ( ? ) v dd = 2.7v, v ss = 0v t a = 25c 02794-012 figure 11. wiper on resistance vs. code temperature (c) 4 ?40 ?20 0 20 40 60 100 3 ?1 80 1 0 2 i dd (a) i dd @ v dd /v ss = 5v/0v i ss @ v dd /v ss = 5v/0v i dd @ v dd /v ss = 2.7v/0v i ss @ v dd /v ss = 2.7v/0v 02794-013 figure 12. i dd vs. temperature, r ab = 10 k midscale clock frequency (mhz) 0.30 024681012 0.25 0.05 0 0.15 0.10 0.20 i dd (ma) zero scale full scale v dd = 5v v ss = 5v 02794-014 figure 13. i dd vs. clock frequency, r ab = 10 k frequency (hz) gain (db) 3 1k 1m ?6 ?12 ?3 ?9 0 10k 100k v dd @ v ss = 2.5v v a = 1v rms d = midscale f ?3db = 66khz f ?3db = 600khz, r ab = 10k ? f ?3db = 132khz, r ab = 50k ? 02794-015 figure 14. ?3 db bandwidth vs. resistance (using the circuit shown in figure 31) frequency (hz) thd + noise (%) 0.05 10 100k 0.02 0 0.03 0.01 0.04 100 1k 10k r ab = 10k ? v dd /v ss = 2.5v v a = 1v rms r ab = 50k ? r ab = 100k ? 02794-016 figure 15. total harmonic distortion + noise vs. frequency frequency (hz) gain (db) 0 100 10m ?30 ?42 ?24 ?36 ?12 1k 10k 100k ?6 ?18 1m 0x01 0x02 0x04 0x08 0x10 code 0x20 0 2794-017 figure 16. gain vs. frequency vs. code, r ab = 10 ( figure 31)
ad5233 rev. b | page 11 of 32 frequency (hz) gain (db) 0 100 1m ?30 ?42 ?24 ?36 ?12 1k 10k 100k ?6 ?18 code 0x20 0x10 0x08 0x04 0x02 0x01 0 2794-018 figure 17. gain vs. frequency vs. code, r ab = 50 k ( figure 31 ) frequency (hz) gain (db) 0 100 1m ?30 ?42 ?24 ?36 ?12 1k 10k 100k ?6 ?18 code 0x20 0x10 0x08 0x04 0x02 0x01 02794-019 figure 18. gain vs. frequency vs. code, r ab = 100 k ( figure 31 ) frequency (hz) psrr (db) 80 100 10m 1m 30 0 10 40 20 60 1k 10k 100k 70 50 v dd = 5v 100mv ac v ss = 0v, v a = 5v, v b = 0v measured at v w with code = 0x200 r ab = 100k ? r ab = 50k ? r ab = 10k ? 02794-020 figure 19. psrr vs. frequency midscale expected value 100s/div v dd = 5v v a = 2.25v v b = 0v v a v w 0.5v/ div 0 2794-021 figure 20. power-on reset, v a = 2.25 v, v b = 0 v, code = 101010 time (s) 2.60 2.58 2.56 0 50 100 250 350 450 200150 300 400 511 2.54 2.52 2.42 2.40 2.46 2.44 2.50 2.48 v out (v) v dd = v a = 5v v ss = v b = 0v code = 0x20 to 0x1f 02794-022 figure 21. midscale glitch energy, code 0x20 to code 0x1f clk sdi i dd 20ma/ div 4ms/div 5v/div 5v/div 5v/div cs 02794-023 figure 22. i dd vs. time when storing data to eemem
ad5233 rev. b | page 12 of 32 clk sdi i dd * 2ma/div *supply current returns to minimum power consumption, if instruction 0 (nop) is executed immediately after instruction 1 (read eemem). 4ms/div 5v/di v 5v/div 5v/div cs 02794-024 1 0.01 0.1 code (decimal) theoretical, i wb_max (ma) 0 8 16 24 32 40 48 56 64 10 100 r ab = 10k ? r ab = 100k ? r ab = 50k ? v a = v b = open t a = 25c 02794-025 figure 23. i dd vs. time when reading data from eemem figure 24. i wb_max vs. code
ad5233 rev. b | page 13 of 32 test circuits figure 25 to figure 35 define the test conditions used in the specifications. a w b nc i w dut v ms nc = no connect 02794-026 figure 25. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) a w b dut v ms v+ v + = v dd 1lsb = v+/2 n 0 2794-027 figure 26. potentiometer divider nonlinearity error (inl, dnl) a w b dut i w v ms1 v ms2 v w r w = [v ms1 ? v ms2 ]/i w 0 2794-028 figure 27. wiper resistance a w b v ms v+ = v dd 10% psrr (db) = 20 log v a v dd pss (%/%) = v ms % v dd % v ms v dd () v+ 02794-029 figure 28. power supply sensitivity (pss, psrr) offset bias offset gnd a dut b w 5v v in v out op279 02794-030 figure 29. inverting gain offset bias offset gnd ab dut w 5 v v in v out op279 0 2794-031 figure 30. noninverting gain offset gnd a b dut w +15 v v in v out op42 ?15v 2.5v 02794-032 figure 31. gain vs. frequency + dut code = 0x00 0.1v v bias r sw = 0.1 v i sw i sw w b a = nc ? 02794-033 figure 32. incremental on resistance
ad5233 rev. b | page 14 of 32 dut v ss i cm w b v dd nc nc v cm gnd a nc = no connect 02794-034 figure 33. common-mode leakage current v in a1 rdac1 w1 b1 nc nc = no connect v ss v dd a2 rdac2 w2 b2 v out c ta = 20 log v out v in () 02794-035 figure 34. analog crosstalk 200a i ol 200a i oh v oh (min) or v ol (max) to output pin c l 50pf 0 2794-036 figure 35. load circuit for measuring v oh and v ol ; the diode bridge test circuit is equivalent to the application circuit with r pull-up of 2.2 k
ad5233 rev. b | page 15 of 32 theory of operation the ad5233 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of v ss < v term < v dd . the basic voltage range is limited to v dd ? v ss < 5.5 v. the digital potentiometer wiper position is determined by the rdac register contents. the rdac register acts as a scratchpad register, allowing as many value changes as necessary to place the potentiometer wiper in the correct position. the scratchpad register can be programmed with any position value using the standard spi serial interface mode by loading the complete representative data-word. once a desirable position is found, this value can be stored in an eemem register. thereafter, the wiper position is always restored to that position for subsequent power-up. the eemem data storing process takes approximately 25 ms; during this time, the shift register is locked, preventing any changes from taking place. the rdy pin pulses low to indicate the completion of this eemem storage. the following instructions facilitate the users programming needs (see tabl e 7 for details): 0 = do nothing. 1 = restore eemem contents to rdac. 2 = store rdac setting to eemem. 3 = store rdac setting or user data to eemem. 4 = decrement 6 db. 5 = decrement all 6 db. 6 = decrement one step. 7 = decrement all one step. 8 = reset eemem contents to rdacs. 9 = read eemem contents from sdo. 10 = read rdac wiper setting from sdo. 11 = write data to rdac. 12 = increment 6 db. 13 = increment all 6 db. 14 = increment one step. 15 = increment all one step. scratchpad and eem em programming the scratchpad rdac register directly controls the position of the digital potentiometer wiper. for example, when the scratchpad register is loaded with all 0, the wiper is connected to terminal b of the variable resistor. the scratchpad register is a standard logic register with no restriction on the number of changes allowed, but the eemem registers have a program erase/write cycle limitation (see the flash/eemem reliability section). basic operation the basic mode of setting the variable resistor wiper position (programming the scratchpad register) is accomplished by loading the serial data input register with instruction 11, address a1, address a0, and the desired wiper position data. when the proper wiper position is determined, the user can load the serial data input register with instruction 2, which stores the wiper position data in the eemem register. after 25 ms, the wiper position is permanently stored in the nonvolatile memory location. table 5 provides a programming example listing the sequence of serial data input (sdi) words with the serial data output appearing at the sdo pin in hexadecimal format. table 5. set and store rdac data to eemem register sdi sdo action 0xb010 0xxxxx writes data 0x10 to the rdac1 register, wiper w1 moves to ? full-scale position. 0x20xx 0xb010 stores rdac1 register content into the eemem1 register. at system power-on, the scratchpad register is automatically refreshed with the value previously stored in the eemem register. the factory-preset eemem value is midscale, but it can be changed by the user thereafter. during operation, the scratchpad (rdac) register can be refreshed with the eemem register data with instruction 1 or instruction 8. the rdac register can also be refreshed with the eemem register data under hardware control by pulsing the pr pin. the pr pulse first sets the wiper at midscale when brought to logic 0, and then, on the positive transition to logic 1, it reloads the rdac wiper register with the contents of eemem. many additional advanced programming commands are available to simplify the variable resistor adjustment process (see table 7 ). for example, the wiper position can be changed one step at a time using the increment/decrement instruction or by 6 db with the shift left/right instruction. once an increment, decrement, or shift instruction has been loaded into the shift register, subsequent cs strobes can repeat this command. a serial data output sdo pin is available for daisy-chaining and for readout of the internal register contents.
ad5233 rev. b | page 16 of 32 eemem protection the write protect ( wp ) pin disables any changes to the scratchpad register contents, except for the eemem setting, which can still be restored using instruction 1, instruction 8, and the pr pulse. therefore, wp can be used to provide a hardware eemem protection feature. to disable wp , it is recommended to execute a nop instruction before returning wp to logic 1. digital input/outp ut configuration all digital inputs are esd-protected, high input impedance that can be driven directly from most digital sources. active at logic 0, pr and wp must be tied to v dd if they are not used. no internal pull-up resistors are present on any digital input pins. because the device can be detached from the driving source once it is programmed, adding pull-up resistance on the digital input pins is a good way to avoid falsely triggering the floating pins in a noisy environment. the sdo and rdy pins are open-drain digital outputs that need pull-up resistors only if these functions are used. use a resistor in the range of 1 k to 10 k to balance the power and switching speed trade-off. serial data interface the ad5233 contains a 4-wire spi-compatible digital interface (sdi, sdo, cs , and clk). it uses a 16-bit serial data-word loaded msb first. the format of the spi-compatible word is shown in . the chip-select table 6 cs pin must be held low until the complete data-word is loaded into the sdi pin. when cs returns high, the serial data-word is decoded according to the instructions in . the command bits (cx) control the operation of the digital potentiometer. the address bits (ax) determine which register is activated. the data bits (dx) are the values that are loaded into the decoded register. to program rdac1 to rdac4, only the 6 lsb data bits are used. table 7 the ad5233 has an internal counter that counts a multiple of 16 bits (a frame) for proper operation. for example, the ad5233 works with a 32-bit word, but it cannot work properly with a 15-bit or 17-bit word. in addition, the ad5233 has a subtle feature that, if cs is pulsed without clk and sdi, the part repeats the previous command (except during power-up). as a result, care must be taken to ensure that no excessive noise exists in the clk or cs line that might alter the effective number- of-bits pattern. also, to prevent data from locking incorrectly (due to noise, for example), the counter resets, if the count is not a multiple of four when cs goes high. valid command command processor and address decode (for daisy chain only) serial register clk sdi 5v r pull-up sdo gnd pr wp cs ad5233 counter 02794-037 figure 36. equivalent digital input-output logic the equivalent serial data input and output logic is shown in figure 36 . the open-drain output sdo is disabled whenever chip select ( cs ) is in logic 1. the spi interface can be used in two slave modes: cpha = 1, cpol = 1 and cpha = 0, cpol = 0. cpha and cpol refer to the control bits that dictate spi timing in the following microconverters? and microprocessors: , , m68hc11, and mc68hc16r1/mc68hc916r1. esd protection of the digital inputs is shown in and . aduc812 aduc824 figure 37 figure 38 logic pins v dd gnd input 300 ? 02794-038 figure 37. equivalent esd digital input protection v dd gnd input 300? wp 02794-039 figure 38. equivalent wp input protection
ad5233 rev. b | page 17 of 32 daisy-chain operation the ground pin of the ad5233 device is used primarily as a digital ground reference, which needs to be tied to the pcbs common ground. the digital input control signals to the ad5233 must be referenced to the device ground pin (gnd) and satisfy the logic level defined in the specifications section. an internal level-shift circuit ensures that the common-mode voltage range of the three terminals extends from v ss to v dd , regardless of the digital input level. the serial data output (sdo) pin serves two purposes. it can be used to read the contents of the wiper setting and eemem values using instruction 10 and instruction 9, respectively. the remaining instructions (0 to 8, 11 to 15) are valid for daisy-chaining multiple devices in simultaneous operations. daisy-chaining minimizes the number of port pins required from the controlling ic ( figure 39 ). the sdo pin contains an open-drain n-channel fet that requires a pull-up resistor, if this function is used. as shown in figure 39 , users need to tie the sdo pin of one package to the sdi pin of the next package. power-up sequence because there are diodes to limit the voltage compliance at terminal a, terminal b, and terminal w (see figure 40 ), it is important to power on v dd /v ss first before applying any voltage to te r m i n a l a , te r m i n a l b, a nd te r m i n a l w. o t he r w i s e, t he diode is forward-biased such that v dd /v ss are powered unin- tentionally. for example, applying 5 v across the a and b terminals prior to v dd causes the v dd terminal to exhibit 4.3 v. it is not destructive to the device, but it might affect the rest of the system. the ideal power-up sequence is gnd, v dd , v ss , digital inputs, and v a /v b /v w . the order of powering v a , v b , v w , and digital inputs is not important as long as they are powered after v dd /v ss . users might need to increase the clock period, because the pull-up resistor and the capacitive loading at the sdo to sdi interface might require an additional time delay between subsequent packages. when two ad5233s are daisy-chained, 32 bits of data is required. the first 16 bits go to u2 and the second 16 bits go to u1. cs should be kept low until all 32 bits are clocked into their respective serial registers. cs is then pulled high to complete the operation. sdi sdo clk r p 2k? sdi sdo clk u1 u2 ad5233 ad5233 cs cs + v 0 2794-040 micro- controller regardless of the power-up sequence and the ramp rates of the power supplies, once v dd /v ss are powered, the power-on preset remains effective, which restores the eemem values to the rdac registers. latched digital outputs a pair of digital outputs, o1 and o2, is available on the ad5233. these outputs provide a nonvolatile logic 0 or logic 1 setting. o1 and o2 are standard cmos logic outputs, shown in figure 41 . these outputs are ideal to replace the functions often provided by dip switches. in addition, they can be used to drive other standard cmos logic-controlled parts that need an occasional setting change. pin o1 and pin o2 default to logic 1, and they can drive up to 50 ma of load at 5 v/25c. figure 39. daisy-chain configuration using sdo terminal voltage operation range the ad5233s positive v dd and negative v ss power supplies define the boundary conditions for proper 3-terminal digital potentiometer operation. supply signals present on terminal a, te r m i n a l b, and te r m i n a l w t h at e xc e e d v dd or v ss are clamped by the internal forward-biased diodes (see figure 40 ). v dd gnd outputs o1 and o2 pins 02794-042 v ss v dd a w b 02794-041 figure 41. logic output o1 and logic output o2 figure 40. maximum terminal voltages set by v dd and v ss
ad5233 rev. b | page 18 of 32 in table 6, c0 to c3 are command bits, a3 to a0 are address bits, d0 to d5 are data bits that are applicable to the rdac wiper register, and d0 to d7 are applicable to the eemem register. table 6. 16-bit serial data-word msb instruction byte lsb data byte rdac c3 c2 c1 c0 0 0 a1 a0 x x d5 d4 d3 d2 d1 d0 eemem c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 command instruction codes are defined in table 7. table 7. instruction/operation truth table 1, 2, 3 inst. no. instruction byte 0 data byte 0 operation b16 b8 b7 b6 b5 b4 b3 b2 b1 b0 c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 x x x x x x x x x x x x nop: do nothing. see table 14 for programming example. 1 0 0 0 1 0 0 a1 a0 x x x x x x x x restore eemem contents to the rdac register. this command leaves the device in read program power state. to return the part to the idle state, perform nop instruction 0. see table 14. 2 0 0 1 0 0 0 a1 a0 x x x x x x x x store wiper setting: store rdac (addr) setting to eemem. see table 13. 3 4 0 0 1 1 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 store contents of serial register data byte 0 (total eight bits) to eemem (addr). see table 16. 4 5 0 1 0 0 0 0 a1 a0 x x x x x x x x decrement 6 db: right-shift contents of rdac register, stop at all 0s. 5 5 0 1 0 1 x x x x x x x x x x x x decrement all 6 db: right-shift contents of all rdac registers, stop at all 0s. 6 5 0 1 1 0 0 0 a1 a0 x x x x x x x x decrement content of rdac register by 1, stop at all 0s. 7 5 0 1 1 1 x x x x x x x x x x x x decrement contents of all the rdac registers by 1, stop at all 0s. 8 1 0 0 0 x x x x x x x x x x x x reset: refresh all rdacs with their corresponding eemem previously stored values. 9 1 0 0 1 a3 a2 a1 a0 x x x x x x x x read content of eemem (addr) from sdo output in the next frame. see table 17. 10 1 0 1 0 0 0 a1 a0 x x x x x x x x read rdac wiper setting from sdo output in the next fr ame. see table 18. 11 1 0 1 1 0 0 a1 a0 x x d5 d4 d3 d2 d1 d0 write contents of serial register data byte 0 (total six bits) to rdac. see table 12. 12 5 1 1 0 0 0 0 a1 a0 x x x x x x x x increment 6 db: left-shift contents of rdac register, stop at all 1s. see table 15. 13 5 1 1 0 1 x x x x x x x x x x x x increment all 6 db: left-shift contents of rdac registers, stop at all 1s. 14 5 1 1 1 0 0 0 a1 a0 x x x x x x x x increment contents of the rdac register by 1, stop at all 1s. see table 13. 15 5 1 1 1 1 x x x x x x x x x x x x increment contents of all rdac registers by 1, stop at all 1s. 1 the sdo output shifts out the last 16 bits of data clocked into the serial register for daisy-chain operation. exception: for any instruction follow ing instruction 9 or instruction 10, see details of these instructions for proper usage. 2 the rdac register is a volatile scratchpad register that is automatically refreshed at power-on from the corresponding nonvola tile eemem register. 3 execution of these operations takes place when the cs strobe returns to logic 1. 4 instruction 3 writes one data byte (eight bits of data) to eemem. in the case of address 0, address 1, address 2, and address 3, only the last six bits are valid for wiper position setting. 5 the increment, decrement, and shift instructions ignore the contents of the shift register data byte 0.
ad5233 rev. b | page 19 of 32 advanced control modes t he ad5233 digital potentiometer includes a set of user programming features to address the wide number of applications for these universal adjustment devices. k ey programming features include ? scratchpad programming to any desirable values ? nonvolatile memory storage of the scratchpad rdac register value in the eemem register ? increment and decrement instructions for the rdac wiper register ? left- and right-bit shift of the rdac wiper register to achieve 6 db level changes ? eleven extra bytes of user-addressable nonvolatile memory linear increment and decrement instructions the increment and decrement instructions (14, 15, 6, and 7) are useful for linear step-adjustment applications. these com- mands simplify microcontroller software coding by allowing the controller to send just an increment or decrement command to the device. for an increment command, executing instruction 14 with the proper address automatically moves the wiper to the next resistance segment position. instruction 15 performs the same function, except that the address does not need to be specified. all rdacs are changed at the same time. logarithmic taper mode adjustment four programming instructions produce logarithmic taper increment and decrement of the wiper. these settings are activated by the 6 db increment and 6 db decrement instruc- tions (12, 13, 4, and 5). for example, starting at zero scale, executing the increment instruction 12 seven times moves the wiper in 6 db per step from 0% to full scale, r ab . the 6 db increment instruction doubles the value of the rdac register contents each time the command is executed. when the wiper position is near the maximum setting, the last 6 db increment instruction causes the wiper to go to the full-scale 63 10 code position. further 6 db per increment instructions do not change the wiper position beyond its full scale. the 6 db step increments and 6 db step decrements are achieved by shifting the bit internally to the left or right, respectively. the following information explains the nonideal 6 db step adjustment under certain conditions. tabl e 8 illustrates the operation of the shifting function on the rdac register data bits. each table row represents a successive shift operation. note that the left-shift 12 and 13 instructions were modified such that, if the data in the rdac register is equal to zero and the data is shifted left, the rdac register is then set to code 1. similarly, if the data in the rdac register is greater than or equal to midscale and the data is shifted left, then the data in the rdac register is automatically set to full scale. this makes the left-shift function as ideal a logarithmic adjustment as possible. the right-shift 4 and 5 instructions are ideal only if the lsb is 0 (ideal logarithmic = no error). if the lsb is a 1, the right-shift function generates a linear half-lsb error, which translates to a number-of-bits-dependent logarithmic error, as shown in figure 42 . the plot shows the error of the odd numbers of bits for the ad5233. table 8. detail left-shift and right-shift functions for 6 db step increment and decrement left-shift (+6 db/step) right-shift (C6 db/step) 00 0000 11 1111 00 0001 01 1111 00 0010 00 1111 00 0100 00 0111 00 1000 00 0011 01 0000 00 0001 10 0000 00 0000 11 1111 00 0000 11 1111 00 0000 actual conformance to a logarithmic curve between the data contents in the rdac register and the wiper position for each right-shift 4 and 5 command execution contains an error only for odd numbers of bits. even numbers of bits are ideal. the graph in figure 42 shows plots of log error [20 log 10 (error/ code)] for the ad5233. for example, code 3 log error = 20 log 10 (0.5/3) = ?15.56 db, which is the worst-case scenario. the plot of log error is more significant at the lower codes. code (decimal) 0 0 error (db) ?10 ?50 ?40 ?30 ?20 ?15.56db @ code 3 5 101520253035404550556065 02794-043 figure 42. plot of log error conformance for odd numbers of bits only (even numbers of bits are ideal)
ad5233 rev. b | page 20 of 32 using additional internal nonvolatile eemem the ad5233 contains additional user eemem registers for storing any 8-bit data. table 9 provides an address map of the internal storage registers shown in the functional block diagram as eemem1, eemem2, and 11 bytes of user eemem. table 9. eemem address map eemem umber address eemem content 1 0000 rdac1 1, 2 2 0001 rdac2 1, 2 3 0010 rdac3 1, 2 4 0011 rdac4 1, 2 5 0100 o1 and o2 3 6 0101 user1 4 7 0110 user2 15 1110 user10 16 1111 user11 1 rdac data stored in the eemem location is transferred to the rdac register at power-on, or wh en instruction 1, instruction 8, and pr are executed. 2 execution of instruction 1 leaves the device in the read mode power consumption state. after the last instruction 1 is executed, the user should perform a nop, instruction 0, to return the device to the low power idling state. 3 o1 and o2 data stored in eemem locations is transferred to the corresponding digital register at powe r-on, or when instruction 1 and instruction 8 are executed. 4 userx are internal nonvolatile eemem registers available to store and retrieve constants and other 8-bit information using instruction 3 and instruction 9, respectively. rdac structure the patent-pending rdac contains multiple strings of equal resistor segments, with an array of analog switches that act as the wiper connection. the number of positions is the resolution of the device. the ad5233 has 64 connection points, allowing it to provide better than 1.5% set ability resolution. figure 43 shows an equivalent structure of the connections between the three terminals of the rdac. the sw a and sw b are always on, while the switches, sw(0) to sw(2 n ?1), are on, one at a time, depending on the resistance position decoded from the data bits. because the switch is not ideal, there is a 15 wiper resistance, r w . wiper resistance is a function of supply voltage and temperature. the lower the supply voltage or the higher the temperature, the higher the resulting wiper resistance. users should be aware of the wiper resistance dynamics if an accurate prediction of the output resistance is needed. sw (1) sw (0) sw b b sw a sw(2 n ? 1) sw(2 n ? 2) a w rdac wiper register and decoder r s = r ab /2 n r s r s r s digital c ircuitry o mitted for c larity 0 2794-044 figure 43. equivalent rdac structure programming the variable resistor rheostat operation the nominal resistance of the rdac between terminal a and terminal b, r ab , is available with 10 k, 50 k, and 100 k with 64 positions (6-bit resolution). the final digit(s) of the part number determine the nominal resistance value, for example, 10 = 10 k; 50 = 50 k; 100 = 100 k. the 6-bit data-word in the rdac latch is decoded to select one of the 64 possible settings. the following discussion describes the calculation of resistance (r wb ) at different codes of a 10 k part. for v dd = 5 v, the wipers first connection starts at terminal b for data 0x00. r wb (0) is 15 because of the wiper resistance and because it is independent of the nominal resistance. the second connection is the first tap point, where r wb (1) becomes 156 + 15 = 171 for data 0x01. the third connection is the next tap point, representing r wb (2) = 321 + 15 = 327 for data 0x02, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at r wb (63) = 9858 . see figure 43 for a simplified diagram of the equivalent rdac circuit. when r wb is used, terminal a can be left floating or tied to the wiper. code (decimal) 100 75 0 06 16 r wa (d), 4 r wb (d) (% of full-scale r ab ) 32 48 50 25 r wb r wa 0 2794-045 figure 44. r wa (d) and r wb (d) vs. decimal code
ad5233 rev. b | page 21 of 32 the general equation that determines the programmed output resistance between w and b is w ab wb rr d dr += 64 )( (1) where: d is the decimal equivalent of the data contained in the rdac register. r ab is the nominal resistance between terminal a and terminal b. r w is the wiper resistance. for example, the output resistance values in table 10 are set for the given rdac latch codes with v dd = 5 v (applies to r ab = 10 k digital potentiometers). table 10. r wb (d) at selected codes for r ab = 10 k d (decimal) r wb (d) () output state 63 9858 full scale 32 5015 midscale 1 171 1 lsb 0 15 zero scale (wiper contact resistor) note that in the zero-scale condition a finite wiper resistance of 15 is present. care should be taken to limit the current flow between w and b in this state to no more than 20 ma to avoid degradation or possible destruction of the internal switches. like the mechanical potentiometer that the rdac replaces, the ad5233 part is totally symmetrical. the resistance between wiper w and terminal a also pr oduces a digitally controlled complementary resistance, r wa . figure 44 shows the symmetrical programmability of the various terminal connections. when r wa is used, terminal b can be left floating or tied to the wiper. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. the general transfer equation for this operation is w ab wa rr d dr + ? = 64 64 )( (2) for example, the output resistance values in table 11 are set for the rdac latch codes with v dd = 5 v (applies to r ab = 10 k digital potentiometers). table 11. r wa (d) at selected codes for r ab = 10 k d (decimal) r wa (d) () output state 63 171 full scale 32 5015 midscale 1 9858 1 lsb 0 10015 zero scale channel-to-channel r ab matching is better than 1%. the change in r ab with temperature has a 600 ppm/c temperature coefficient. programming the potentiometer divider voltage output operation the digital potentiometer can be configured to generate an output voltage at the wiper terminal that is proportional to the input voltages applied to terminal a and terminal b. for e x ampl e, c on ne c t i ng te r m i n a l a to 5 v a nd te r m i n a l b to ground produces an output voltage at the wiper that can be any value from 0 v to 5 v. each lsb of voltage is equal to the voltage applied across terminal a and terminal b divided by the 2 n position resolution of the potentiometer divider. because ad5233 can also be supplied by dual supplies, the general equation defining the output voltage at v w with respect to ground for any given input voltages applied to the a and b terminals is b ab w vv d dv += 64 )( (3) equation 3 assumes that v w is buffered so that the effect of wiper resistance is minimized. operation of the digital potenti- ometer in divider mode results in more accurate operation over temperature. here, the output voltage is dependent on the ratio of the internal resistors and not the absolute value; therefore, the drift improves to 15 ppm/c. there is no voltage polarity restriction among the a, b, and w terminals as long as the terminal voltage (v term ) stays within v ss < v term < v dd . programming eamples the following programming examples illustrate a typical sequence of events for various features of the ad5233. see table 7 for the instructions and data-word format. the instruction numbers, addresses, and data appearing at the sdi and sdo pins are in hexadecimal format. table 12. scratchpad programming sdi sdo action 0xb010 0xxxxx writes data 0x10 into rdac register, wiper w1 moves to ? full-scale position. table 13. incrementing rdac1 followed by storing the wiper setting to eemem1 sdi sdo action 0xb010 0xxxxx writes data 0x10 into rdac register, wiper w1 moves to ? full-scale position. 0xe0xx 0xb010 increments the rdac register by one to 0x11. 0xe0xx 0xe0xx increments the rdac register by one to 0x12. continues until desired wiper position is reached. 0x20xx 0xxxxx stores the rdac register data into eemem1. optionally tie wp to gnd to protect eemem values.
ad5233 rev. b | page 22 of 32 the eemem1 value for rdac1 can be restored by power-on, by strobing the pr pin, or by programming, as shown in . table 14 table 14. restoring the eemem1 value to the rdac1 register sdi e ndurance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles. in real terms, a single endurance cycle is composed of the following four independent, sequential events: ? initial page erase sequence sdo action 0x10xx ? read/verify sequence 0xxxxx restores the eemem1 value to the rdac1 register. 0x00xx ? byte program sequence ? second read/verify sequence 0x10xx nop. recommended step to minimize power consumption. during reliability qualification, flash/ee memory is cycled from 0x00 to 0x3f until a first fail is recorded, signifying the endurance limit of the on-chip flash/ee memory. table 15. using left-shift by one to increment 6 db step sdi sdo action 0xc0xx as indicated in the specifications section, the ad5233 flash/ee memory endurance qualification has been carried out in accordance with jedec specification a117 over the industrial temperature range of ?40c to +85c. the results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25c. 0xxxxx moves the wiper to double the present data contained in the rdac1 register. table 16. storing additional user data in eemem sdi sdo action 0x35aa 0xxxxx stores data 0xaa in the extra eemem6 location, user1. (allowable to address in 11 locations with a maximum of eight bits of data.) 0x3655 retention quantifies the ability of the flash/ee memory to retain its programmed data over time. again, the ad5233 has been qualified in accordance with the formal jedec retention lifetime specification (a117) at a specific junction temperature (t j = 55c). as part of this qualification procedure, the flash/ee memory is cycled to its specified endurance limit, described previously, before data retention is characterized. this means that the flash/ee memory is guaranteed to retain its data for its full specified retention lifetime every time the flash/ee memory is reprogrammed. it should also be noted that retention lifetime, based on an activation energy of 0.6 ev, derates with t j as shown in figure 45 . for example, the data is retained for 100 years at 55c operation, but reduces to 15 years at 85c operation. beyond these limits, the part must be reprogrammed so that the data can be restored. 0x35aa stores data 0x55 in the extra eemem7 location user2. (allowable to address in 11 locations with a maximum of eight bits of data.) table 17. reading back data from memory locations sdi sdo action 0x95xx 0xxxxx prepares data read from user1 eemem location. 0x00xx 0x95aa nop instruction 0 sends a 16-bit word out of sdo, where the last eight bits contain the contents of the user1 location. the nop command ensures that the device returns to the idle power dissipation state. t j junction temperature (c) 300 250 0 40 retention (years) table 18. reading back wiper settings sdi sdo action 0xb020 0xxxxx writes rdac1 to midscale. 0xc0xx 0xb020 doubles rdac1 from midscale to full scale (left-shift instruction). 0xa0xx 200 150 100 50 0xc0xx prepares reading the wiper setting from the rdac1 register. 0xxxxx 0xa03f reads back full-scale value from sdo. flash/eemem reliability t he flash/ee memory array on the ad5233 is fully qualified for two key flash/ee memory characteristics, flash/ee memory cycling endurance, and flash/ee memory data retention. 50 60 70 80 90 100 110 analog devices typical performance at t j = 55c 02794-046 figure 45. flash/ee memory data retention
ad5233 rev. b | page 23 of 32 applications information bipolar operation from dual supplies the ad5233 can be operated from dual supplies 2.5 v, which enables control of ground-referenced ac signals or bipolar opera- tion. ac signals as high as v dd /v ss can be applied directly a c ro ss te r m i n a l a an d te r m i n a l b w it h output t a ke n f rom te r m i n a l w. s e e figure 46 for a typical circuit connection. 2.5v p-p ad5233 v ss gnd sdi clk ss sclk mosi gnd micro- converter 1.25v p-p v dd v dd +2.5 v ?2.5v cs d = midscale a w b 02794-047 figure 46. bipolar operat ion from dual supplies gain control compensation a digital potentiometer is commonly used in gain control such as the noninverting gain amplifier shown in figure 47 . u1 v o r2 100k ? v i r1 33.2k ? c1 35pf w ba c2 10pf 02794-048 figure 47. typical noninverting gain amplifier when rdac b terminal parasitic capacitance is connected to the op amp noninverting node, it introduces a 0 for the 1/b o term with 20 db/dec, while a typical op amp gbp has ?20 db/dec characteristics. a large r2 and finite c1 can cause this zeros frequency to fall well below the crossover frequency. therefore, the rate of closure becomes 40 db/dec, and the system as a 0 phase margin at the crossover frequency. the output can ring or oscillate if an input is a rectangular pulse or step function. similarly, it is also likely to ring when switching between two gain values; this is equivalent to a stop change at the input. depending on the op amp gbp, reducing the feedback resistor might extend the zeros frequency far enough to overcome the problem. a better approach is to include a compensation capacitor, c2, to cancel the effect caused by c1. optimum compensation occurs when r1 c1 = r2 c2. this is not an option because of the variation of r2. as a result, one can use the previous relationship and scale c2 as if r2 were at its maximum value. doing this might over- compensate and compromise the performance when r2 is set at low values. on the other hand, it avoids the ringing or oscillation at the worst case. for critical applications, c2 should be found empirically to suit the need. in general, c2 in the range of picofarads is usually adequate for the compensation. similarly, w and a terminal capacitances are connected to the output (not shown); their effect at this node is less significant and the compensation can be avoided in most cases. high voltage operation the digital potentiometer can be placed directly in the feedback or input path of an op amp for gain control, provided that the voltage across terminal a and terminal b, terminal w and te r m i n a l a , or te r m i n a l w a n d te r m i n a l b d o e s not e x c e e d |5 v|. when high voltage gain is needed, users should set a fixed gain in an op amp operated at high voltage and let the digital potentiometer control the adjustable input. figure 48 shows a simple implementation. r2 r 5v a d5233 a w b 15v v+ v? v o 0 to 15v a2 ? + c 0 2794-049 figure 48. 5 v voltage span control similarly, a compensation capacitor, c, might be needed to dampen the potential ringing when the digital potentiometer changes steps. this effect is prominent when stray capacitance at the inverted node is augmented by a large feedback resistor. usually, a capacitor (c) of a few picofarads, is adequate to combat the problem. dac figure 49 shows a unipolar 8-bit dac using the ad5233. the buffer is needed to drive various loads. ad5233 v+ v? ad8601 w a1 v in v out gnd ad1582 5v 5 v u1 3 a b v o 1 2 02794-050 figure 49. unipolar 8-bit dac
ad5233 rev. b | page 24 of 32 bipolar programmable gain amplifier there are several ways to achieve bipolar gain. figure 50 shows one versatile implementation. digital potentiometer, u1, sets the adjustment range; therefore, the wiper voltage, v w2 , can be programmed between v i and ?kv i at a given u2 setting. v+ v? op2177 v o v+ v? op2177 ad5233 ad5233 v i a1 w1 b1 ?kv i a2 b2 w2 v dd v ss r1 r2 v dd v ss a1 u2 a2 u1 c 02794-051 figure 50. bipolar programmable gain amplifier configuring a2 as a noninverting amplifier yields a linear transfer function: ? ? ? ? ? ? ?+ ? ? ? ? ? ? += )1( 64 1 (4) where: k is the ratio of r wb /r wa that is set by u1. d is the decimal equivalent of the input code. in the simpler (and much more usual) case where k is 1, a pair of matched resistors can replace u1. equation 4 can be simplified to ? ? ? ? ? ? ? ? ? ? ? ? ? += 1 64 2 1 2 d r1 r2 v v i o (5) table 19 shows the result of adjusting d with a2 configured as a unity gain, a gain of 2, and a gain of 10. the result is a bipolar amplifier with linearly programmable gain and 64-step resolution. table 19. result of bipolar gain amplifier d r1 = , r2 = 0 r1 = r2 r2 = 9 r1 0 ?1 ?2 ?10 16 ?0.5 ?1 ?5 32 0 0 0 48 0.5 1 5 63 0.968 1.937 9.680 programmable low-pass filter the ad5233 digital potentiometer can be used to construct a second-order sallen-key low-pass filter, as shown in figure 51 . a b v i ad8601 +2.5v v o ganged together ?2.5v v+ v? w r r2 r1 a b w r c1 c2 u1 0 2794-052 figure 51. sallen-key low-pass filter the design equations are 2 2 2 o o o i o s q s v v + + = (6) c2c1r2r1 o = 1 (7) c2r2 1 c1r1 q + = 1 (8) where: q is the q factor. v o is the resonant frequency. r1 and r2 are r wb1 and r wb2 , respectively. to achieve maximal flat bandwidth where q is 0.707, let c1 be twice the size of c2 and let r1 equal r2. users can first select convenient values for the capacitors and then gang and move r1 and r2 together to adjust the ?3 db corner frequency. instruction 5, instruction 7, instruction 13, and instruction 15 of the ad5233 make these changes simple to implement.
ad5233 rev. b | page 25 of 32 programmable state-variable filter one of the standard circuits used to generate a low-pass, high- pass, or band-pass filter is the state-variable active filter. the ad5233 digital potentiometer allows full programmability of the frequency, the gain, and the q of the filter outputs. figure 52 shows a filter circuit using a 2.5 v virtual ground, which allows a 2.5 v peak input and output swing. rdac2 and rdac3 set the low-pass, high-pass, and band-pass cutoff and center frequencies, respectively. rdac2 and rdac3 should be programmed with the same data (as with ganged potentiometers) to maintain the best circuit q. a3 a2 a1 0.01f 0.01f rdac3 low-pass band-pass high-pass rdac2 b rdac4 b v in b rdac1 2.5v op279 2 r2 10k ? r1 10k? a3 b 0 2794-053 figure 52. programmable stable-variable filter the transfer function of the band-pass filter is 2 2 o o o o i bp s q s s q a v v z z z (9) where a o is the gain. for r wb2(d2) = r wb3(d3) , r1 = r2, and c1 = c2: c1r wb2 o 1 z (10) wa1 wb1 o r r a (11) r1 r r r q wb1 wb4 wa4 u (12) figure 53 shows the measured filter response at the band-pass output as a function of the rdac2 and rdac3 settings, which produce a range of center frequencies from 2 khz to 20 khz. the filter gain response at the band-pass output is shown in figure 54 . at a center frequency of 2 khz, the gain is adjusted over the ?20 db to +20 db range, determined by rdac1. circuit q is adjusted by rdac4 and rdac1. suitable op amps for this application are op4177, ad8604, op279, and ad824. 40 20 100 1k 10k 100k 200k frequency (hz) amplitude (db) 0 ?20 ?40 ?60 ?80 20 20k ?16 * 02794-054 figure 53. programmed center frequency band-pass response 40 20 100 1k 10k 100k 200k frequency (hz) amplitude (db) 0 ?20 ?40 ?60 ?80 20 2.0k ?19.01 02794-055 figure 54. programmed amplitude band-pass response
ad5233 rev. b | page 26 of 32 programmable oscillator in a classic wien-bridge oscillator, shown in figure 55 , the wien network (r, r, c, c) provides positive feedback, while r1 and r2 provide negative feedback. at the resonant frequency, f o , the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. if the op amp is chosen with a relatively high gain bandwidth product, the frequency response of the op amp can be neglected. +2.5v op1177 v+ v? v o ?2.5v r2a 2.1k ? d1 d2 r2b 10k ? vn r1 1k? ab w r = r' = r2b = 1/4 ad5233 d1 = d2 = 1n4148 c' 2.2nf r' 10k ? ab w vp c 2.2nf r 10k ? a b w u1 amplitude adjustment frequency adjustment 02794-056 figure 55. programmable oscillator with amplitude control with r = r, c = c, and r2 = r2a||(r2b + r diode ), the oscillation frequency is r c o 1 z or r c f o s 2 1 (13) where r is equal to r wa such that ab r d r 64 64 (14) at resonance, setting 2 r1 r2 (15) balances the bridge. in practice, r2/r1 should be set slightly larger than 2 to ensure that the oscillation can start. on the other hand, the alternate turn-on of the diodes, d1 and d2, ensures that r1/r2 is smaller than 2 momentarily and, therefore, stabilizes the oscillation. once the frequency is set, the oscillation amplitude can be turned on by r2b, because d d o vr2biv 3 2 (16) where v o , i d , and v d are interdependent variables. with proper selection of r2b, an equilibrium is reached such that v o converges. r2b can be in series with a discrete resistor to increase the amplitude, but the total resistance cannot be too large or it saturates the output. in this configuration, r2b can be adjusted from minimum to full scale with amplitude varied from 0.6 v to 0.9 v. using 2.2 nf for c and c, 10 k dual digital potentiometer, with r and r set to 8.06 k, 4.05 k, and 670 , oscillation occurs at 8.8 khz, 17.6 khz, and 102 khz, respectively (see figure 56 ). 1v/div r = 8.06k ? f = 8.8khz r = 4.05k ? f = 17.6khz r = 670 ? f = 102khz 1v/div 1v/div 02794-057 figure 56. programmable oscillation in both circuits (shown in figure 51 and figure 55 ), the frequency tuning requires that both rdacs be adjusted to the same settings. because the two channels might be adjusted one at a time, an intermediate state occurs that might not be acceptable for some applications. of course, the increment/ decrement all instructions (5, 7, 13, and 15) can be used. different devices can also be used in daisy-chain mode so that parts can be programmed to the same setting simultaneously. programmable voltage source with boosted output for applications that require high current adjustment, such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see figure 57 ). ad5233 v+ v? w u2 ad8601 a b v in v out r bias i l signal c c ld 2n7002 02794-058 figure 57. programmable boosted voltage source in this circuit, the inverting input of the op amp forces the v out to be equal to the wiper voltage set by the digital potentiometer. the load current is then delivered by the supply via the n- channel fet n 1 . n 1 power handling must be adequate to dissipate (v i ? v o ) i l power. this circuit can source a maximum of 100 ma with a 5 v supply. for precision applications, a voltage reference such as adr421, adr03, or adr370 can be applied at terminal a of the digital potentiometer.
ad5233 rev. b | page 27 of 32 programmable current source a programmable current source can be implemented with the circuit shown in figure 58 . v+ v? op1177 u2 v s sleep ref191 gnd output 3 2 4 6 u1 c1 1f ad5233 w a b r s 102 ? r l 100 ? v l i l +5 v ?2.048v to v l ?5v 0 to (2.048 + v l ) +5v + ? 0 2794-059 figure 58. programmable current source ref191 is a unique low supply headroom precision reference that can deliver the 20 ma needed at 2.048 v. the load current is simply the voltage across terminal b to terminal w of the digital potentiometer divided by r s . the circuit is simple, but be aware that there are two issues. first, dual-supply op amps are ideal, because the ground potential of ref191 can swing from ?2.048 v at zero scale to v l at full scale of the potentiometer setting. although the circuit works under single supply, the programmable resolution of the system is reduced. second, the voltage compliance at v l is limited to 2.5 v or equivalently a 125 load. if higher voltage compliance is needed, users can consider digital potentiometers ad5260, ad5280, and ad7376. figure 58 shows an alternative circuit for high voltage compliance. to achieve higher current, such as when driving a high power led, the user can replace the u1 with an ldo, reduce r s , and add a resistor in series with the ad5233s a terminal. this limits the potentiometers current and enhances the current adjustment resolution. programmable bidirectional current source for applications that require bidirectional current control or higher voltage compliance, a howland current pump can be used (see figure 59 ). ?15v op2177 v+ v? +15v + ? c1 10pf r2 15k? r1 150k ? r2b 50 ? r l 500 ? v l r2a 14.95k ? r1 150k? i l op2177 v+ v? +15v + ? ?15v a1 a d5233 a bw +2.5v ?2.5v a2 02794-060 figure 59. programmable bidirectional current source if the resistors are matched, the load current is w l v r2b r1 r2br2a i u (17) r2b, in theory, can be made as small as necessary to achieve the current needed within the a2 output current-driving capability. in this circuit, op2177 delivers 5 ma in both directions, and the voltage compliance approaches 15 v. without c1, it can be shown that the output impedance is ) ('' )(' r2br2ar1r2r1 r2ar1r2br1 z o u u (18) z o can be infinite if the r1 and r2 resistors match precisely with r1 and r2a + r2b, respectively. on the other hand, z o can be negative if the resistors are not matched. as a result, c1 in the range of 1 pf to 10 pf is needed to prevent oscillation from the negative impedance. resistance scaling ad5233 offers 10 k, 50 k, and 100 k nominal resistance. users who need lower resistance but want to maintain the number of adjustment steps can parallel multiple devices. for example, figure 60 shows a simple scheme of paralleling two ad5233 channels. to adjust half the resistance linearly per step, users need to program both devices concurrently with the same settings. a1 b1 w1 w2 a2 b2 ld v dd 02794-061 figure 60. reduce resistance by half wi th linear adjustment characteristics
ad5233 rev. b | page 28 of 32 in voltage divider mode, by paralleling a discrete resistor as shown in figure 61 , a proportionately lower voltage appears at terminal a to terminal b. this translates into a finer degree of precision because the step size at terminal w is smaller. resistance tolerance, drift, and temperature mismatch considerations r2 r3 v dd r1 b w 0 a 02794-062 figure 61. lowering the nominal resistance the voltage can be found as follows: dd ab ab w v d rrr rr dv + = 64|| )||( )( 2 3 2 (19) in a rheostat mode operation such as gain control (see figure 64 ), the tolerance mismatch between the digital potentiometer and the discrete resistor can cause repeatability issues among various systems. because of the inherent matching of the silicon process, it is practical to apply the dual- or multiple-channel device in this type of application. as such, r1 can be replaced by one of the channels of the digital potentiometer and programmed to a specific value. r2 can be used for the adjustable gain. although it adds cost, this approach minimizes the tolerance and temperature coefficient mismatch between r1 and r2. this approach also tracks the resistance drift over time. as a result, all nonideal parameters become less sensitive to the system variations. ad8601 + ? v i u1 v o c1 ab w r2 r1* *replaced with another channel of rdac 0 2794-065 figure 60 and figure 61 show that the digital potentiometer steps change linearly. on the other hand, log taper adjustment is usually preferred in applications such as audio control. figure 62 shows another type of resistance scaling. in this configuration, the smaller the r2 with respect to r1, the more the pseudo log taper characteristic of the circuit behaves. r1 r2 v o v i a b w 0 2794-063 figure 64. linear gain control with tracking resistance tolerance and temperature coefficient rdac circuit simulation model the internal parasitic capacitances and the external load dominate the ac characteristics of the rdacs. configured as a potentiometer divider, the ?3 db bandwidth of the ad5233 (10 k resistor) measures 370 khz at half scale. figure 14 provides the large signal bode plot characteristics. a parasitic simulation model is shown in figure 65 . figure 62. resistor scaling with pseudo log adjustment characteristics doubling the resolution borrowing from analog devices patented rdac segmentation technique, the user can configure three channels of ad5233, as shown in figure 63 . by paralleling a discrete resistor, r p ( r p = r ab /64), with rdac3, the user can double the resolution of ad5233 from 6 bits to 12 bits. one might think that moving rdac1 and rdac2 together would form the coarse 6-bit resolution, and then moving rdac3 would form the finer 6-bit resolution. as a result, the effective resolution would become 12 bits. however, the precision of this circuit remains only 6-bit accurate and the programming can be complicated. a rdac 10k? w c b 35pf c a 35pf c w 35pf b 02794-066 rdac1 a1 b1 v a w3 rdac3 a3 b3 rdac2 a2 b2 r p 02794-064 figure 65. rdac circuit simulation model for rdac = 10 k the following code provides a macromodel net list for the 10 k rdac: listing i. spice model net list .param d = 64, rdac = 10e3 * .subckt dpot (a, w, b) * ca a 0 35e-12 rwa a w {(1-d/64)* rdac + 15} cw w 0 35-12 rwb w b {d/64 * rdac + 15} cb b 0 35e-12 * .ends dpot figure 63. doubling ad5233 from 6 bits to 12 bits
ad5233 rev. b | page 29 of 32 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 66. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters ordering guide model no. of channels r ab (k ? ) temperature range package description package option ordering quantity branding 1 ad5233bru10 4 10 ?40c to +85c 24-lead tssop ru-24 96 5233b10 ad5233bru10-reel7 4 10 ?40c to +85c 24-lead tssop ru-24 1,000 5233b10 ad5233bruz10 2 4 10 ?40c to +85c 24-lead tssop ru-24 96 5233b10 AD5233BRUZ10-R7 2 4 10 ?40c to +85c 24-lead tssop ru-24 1,000 5233b10 ad5233bru50 4 50 ?40c to +85c 24-lead tssop ru-24 96 5233b50 ad5233bru50-reel7 4 50 ?40c to +85c 24-lead tssop ru-24 1,000 5233b50 ad5233bruz50 2 4 50 ?40c to +85c 24-lead tssop ru-24 96 5233b50 ad5233bruz50-r7 2 4 50 ?40c to +85c 24-lead tssop ru-24 1,000 5233b50 ad5233bru100 4 100 ?40c to +85c 24-lead tssop ru-24 96 5233b100 ad5233bru100-reel7 4 100 ?40c to +85c 24-lead tssop ru-24 1,000 5233b100 ad5233bruz100 2 4 100 ?40c to +85c 24-lead tssop ru-24 96 5233b100 ad5233bruz100-r7 2 4 100 ?40c to +85c 24-lead tssop ru-24 1,000 5233b100 1 line 1 contains the model number. line 2 contains the analog devices logo followed by the end-to-end resistance value. line 3 contains the date code, yww or #yww, for rohs compliant parts. 2 z = rohs compliant part.
ad5233 rev. b | page 30 of 32 notes
ad5233 rev. b | page 31 of 32 notes
ad5233 rev. b | page 32 of 32 notes purchase of licensed i2c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by philips. ?2002C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02794-0-5/08(b)

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